DMA (Direct Memory Access) and its Cycle stealing

Direct Memory Access:

1. Blocks of data are transferred between an external device and the main memory, without continuous intervention by the processor.
2. A DMA controller temporarily
   a.borrows the address bus, data bus, and control bus from the microprocessor and
   b.transfers the data bytes directly between an I/O port and a series of memory locations.
3. Two control signals are used to request and acknowledge a DMA transfer in the microprocessor-based system.
4. The HOLD signal is a bus request signal which asks the microprocessor to release control of the buses after the current bus cycle.
5. The HLDA signal is a bus grant signal which indicates that the microprocessor has indeed released control of its buses by placing the buses at their high-impedance states.
6. The HOLD input has a higher priority than the INTR or NMI interrupt inputs.
7. OS is also responsible for suspending the execution of one program and starting another.
   –OS puts the program that requested the transfer in the Blocked state,
   –initiates the DMA operation,
   –starts execution of another program.
8. When the transfer is complete, the DMA controller informs the processor by sending an interrupt request.
9. OS puts suspended program in the Runnable state so that it can be selected by the scheduler to continue execution.

Cycle Stealing:

1. Requests by DMA devices for using the bus are alwas given higher priority than processor requests.
2. Among different DMA devices, top priority is given to high-speed peripherals (disks, high-speed network interface, graphics display device).
3. Since the processor initiates most memory access cycles, it is often stated that DMA steals memory cycles from the processor (cycle stealing) for its purpose.
4. If DMA controller is given exclusive access to the main memory to transfer a block of data without interruption, this is called block or burst mode.